logo of Engineer.net engineering job board post engineering jobs without the scary price ! home page of engineering jobs
contact for engineering jobs
sitemap of engineer.net engineer job site
Engineering Jobs


Engineering Jobs


easy as 1-2-3..
Post Jobs
Browse Resumes
log-in, register


browse jobs
search jobs
jobs by RSS
jobs on Twitter
entry level jobs
professional level
post your resume
log-in, register


An Interview with
Gerald Celente,
Trends affecting

"An Interview with
Dr. Steve Keen"

"Roller Coaster
Engineer Karl

"Farewell Engineer

"Engineer Career

"Tips to Survive

"On Engineering


Salary Reports


Link to Us

Engineering Jobs

Engineering Jobs sites at TenLinks

engineer job notice

Physical Design Engineer / DFT (Design for testing) Engineer / STA (Static Timing Analysis) Engineer / DV (Design Verification Engineer) / PI (Power Integrity) Engineer - Singapore, Singapore

TroyTech International Consulting Pte Ltd

Bookmark and Share

DFT (Design for testing) Engineer:
• 4-6 years of experience
• Experience with Synopsys Toolset is mandatory.
• Scan insertion, Debug DRC, ATPG patterns
• Gate Level Simulation ( timing and no-timing)
• Knowledge in P1500 and JTAG is an advantage.
• Knowledge in MBIST is an advantage.

Physical Design Engineer:
• 4-6 years of experience
• Cadence EDI experience is mandatory.
• Experience with High-speed design closure techniques.
• Experience with ARM is preferred.

STA (Static Timing Analysis) Engineer:
• 5-7 years or more experience
• Synopsys Primetime is mandatory
• Experience with Timing closure and ECOS preparation.
• Experience with Clear timing concepts.
• Understanding on SDC is an advantage.

DV (Design Verification Engineer):
• 4-5 years’ experience
• Experience with Gate Level Simulations
• Experience with development of CPU verification plan for ARM & MIPS-based CPU/DSP
• Experience with creating reusable Test bench & developing patterns to verify CPU Subsys
• Experience with regression mechanisms development
• Knowledge in Synopsys, Cadence and Mentor Graphics Questa is an advantage.
• Experience with LEC (Logic Equivalence Check)

PI (Power Integrity) Engineer:
• 4~5 years of Power Integrity experience
• Experience with Apache RedHawk
• Experience with Static Power Integrity Simulation & Analysis
• Experience with Dynamic Power Integrity Simulation & Analysis with different functional cases (e.g. MaxPower)
• Experience with Power, Signal Electro Migration Simulation & Analysis

Primary Skills: Physical Design, Synopsys Toolset, Cadence EDI, Synopays Primetime, Gate Level Simulations, Apache Redhawk
Salary: Between -
Experience Required: Experienced, 4 years minimum
Clearance Level: none
Travel: 0 %

Other Details:
Fatal error: Uncaught Error: Call to undefined function ereg_replace() in /home/engineer/www/jobs/engineeringjobs.php:505 Stack trace: #0 {main} thrown in /home/engineer/www/jobs/engineeringjobs.php on line 505